Threshold crossing detector

ABSTRACT

A method and apparatus is disclosed for forming a binary level output signal which has a single transition representative of a threshold crossing in a sensor output signal. The sensor output signal is applied to the inputs of two signal processing circuits, the first of which develops a first signal having a relatively fast transition representing the threshold crossing. The second circuit develops a second output signal that is representative of an integrated version of the sensor signal. In the preferred embodiment, a flip-flop receives the first signal at a clock input and the second signal at a data input. The flip-flop&#39;s set input may also receive the second signal. The resultant output signal from the flip-flop has but a single transition representing the threshold crossing, irrespective of noise-induced threshold crossings in the sensor output signal.

FIELD OF THE INVENTION

This invention is generally directed to circuitry for detecting athreshold crossing in the output signal of a sensor, and for generatinga further, typically binary, signal that is free of noise and thataccurately identifies the threshold crossing.

BACKGROUND OF THE INVENTION

In a prior art threshold detector (sometimes referred to as a"zero-crossing" detector), the output of a sensor is processed bycircuitry such as that shown in FIG. 1.

In the illustrated arrangement, a sensor 10 (such as a reluctancesensor) develops an output signal A which, as shown by waveform A inFIG. 2, is a sinusoidal type signal superimposed on a threshold level V.At time t₁, the signal A crosses the threshold V, thereby generating a"threshold-crossing". In the case where the threshold level V is zerovolts, the transition at t₁ is referred to as a "zero-crossing". Thepurpose of the circuity shown in FIG. 1 is to develop a binary outputsignal that has a single transition (as opposed to multiple, unwantedtransitions) at t₁, and that is substantially free of any noise that maybe superimposed on the signal A.

Referring again to FIG. 1, the signal A is coupled to the input of azero-crossing (or threshold-crossing) detector 12 that generates abinary level output signal B (see waveform B in FIG. 2) having apositive-going transition that occurs at time t₁.

The sensor signal A is also applied to an integrator 14 which applies anintegrated version of the signal A to a threshold detector 16. Theoutput of the detector 16 is a binary signal C (see waveform C in FIG.2). This signal C is applied to the clock (C) input of a flip-flop 18,while the signal B is applied to the reset (R) input of the sameflip-flop.

The purpose of the flip-flop is to generate a noise-free output signal D(see waveform D in FIG. 2) that has an "arm" transition and a "fire"transition. The "arm" transition is included for the purpose ofestablishing an amplitude level from which one can generate the "fire"transition. The "fire" transition is the important one, as it representsthe time when the sensor signal experiences its threshold-crossing. In atypical automotive application, the "fire" transition gets counted, orotherwise used, to form a timing reference for a fuel injector or thelike.

A problem with the foregoing approach is that, in some applications,extra circuitry may be needed to ensure that the integrated sensorsignal (i.e., the signal formed by the integrator 14 and the thresholddetector 16) has a fast enough rise time and/or fall time to reliablyclock the arming of the output signal. In FIG. 1, for example, thesignal applied to the "clock" input of the flip-flop 18 must have arelatively rapid transition in order to reliably clock the flip-flop andthereby generate the "arm" transition shown in waveform D. While in manyapplications the flip-flop can be reliably clocked if the integratedsensor signal is properly processed (such as by including pulse shapingcircuitry within, or in addition to, the threshold detector 16), it ispreferable to derive the output signal differently in order to minimizethe risk of providing an improper "arm" and "fire" type output signal,while at the same time ensuring that the output signal remains free ofmultiple, unwanted transitions.

OBJECTS OF THE INVENTION

It is a general object of the invention to provide an improved methodand apparatus for developing an accurate and reliable output signalrepresentative of a sensor signal's threshold crossing.

It is another object of the invention to provide such an output signalthat does not have multiple, unwanted transitions.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1, previously discussed, shows a prior art threshold detector;

FIG. 2 shows various waveforms produced by the detector of FIG. 1;

FIG. 3 is a schematic diagram of a threshold detector in accordance withthe invention;

FIG. 4 shows waveforms produced by the detector of FIG. 3;

FIG. 5 shows an alternate output logic circuit for use with the detectorof FIG. 3; and

FIG. 6 shows another output logic circuit that may be used with thedetector of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 3, a threshold detector 20 is shown which incorporatesthe features of the invention. This threshold detector includes a sensor22 that generates, at node A, a sensor signal such as that shown bywaveform A of FIG. 4. This waveform depicts one cycle of a sensor signalthat begins at time T₁, undergoes a threshold crossing 28 at T₃, andends at T₅.

A first, conventional signal processing circuit 23, including acomparator 24, receives the sensor signal from node A. The signalprocessing circuit 23 develops, at node C, a first signal (see waveformC of FIG. 4) that has a relatively fast transition 26 that representsthe threshold crossing 28 of the sensor signal. Preferably, only asingle transition 26 will occur, but, as shown, a double transition(indicated by the two vertical lines near time T₃) may result because ofnoise in the sensor signal (waveform A) which can appear as one or morethreshold crossings near the time T₃. Such multiple threshold crossingscan give rise to corresponding multiple transitions in the signal atnode C.

Waveform C is also shown with multiple transitions 30 prior to time T₁,and additional multiple transitions 32 after T₅. The multipletransitions 30 illustrate how noise on the sensor signal at node A canresult in one or more transitions occurring in the signal at node Cprior to time T₁. Likewise, the multiple transitions 32 illustrate hownoise on the sensor signal can result in one or more transitionsoccurring in the signal at node C after time T₅. The important point tounderstand is that there may be multiple, noise-induced transitions inthe signal at node C rather than a single transition at each of thetimes T₁, T₃, and T₅, and these multiple transitions can occur randomly.In spite of these multiple transitions, it is important that thethreshold detector 20 generate an output signal that has only 1transition that represents the threshold crossing of the sensor signal.

Referring again to FIG. 3, a second signal processing circuit 34,including an RC integrator (resistor 36 and capacitor 38) and acomparator 40, receives the sensor signal from node A. This secondsignal processing circuit develops, at node D, a second signal (seewaveform D) that has transitions 42, 44 between a first level (H) and asecond level (L), and that is representative of an integrated version ofthe sensor signal. To develop this output signal, the signal processingcircuit 34 first integrates the sensor signal by means of the RCintegrator to develop, at node B, an integrated signal as shown bywaveform B in FIG. 4. The signal processing circuit 34 then, using thecomparator 40 and its associated circuitry, compares the integratedsignal at node B to a threshold level T, and develops the output signalat node D. As can be seen from waveform D, this output signal undergoesthe transition 42 when the integrated signal (waveform B) exceeds thethreshold level T, and it undergoes the transition 44 when theintegrated signal falls below the threshold level T. It can also be seenthat multiple transitions 42, 44 may occur as the result of noise on theintegrated signal. However, the illustrated embodiment of the inventionprecludes such multiple transitions in waveform D from generatingmultiple transitions in the ultimate output signal (waveform E)developed by the threshold detector 20.

Referring again to FIG. 3, an output logic circuit, shown as a "D-type"flip-flop 46, (e.g., type MC 14013B made by Motorola, Inc.) receives thesignals from nodes C and D to develop an output signal (see waveform E)on an output lead E. According to one aspect of the invention, the firstand second signals (from nodes C and D) are processed so as to: hold theoutput signal (E) at a given level (e.g., level H) while the secondsignal is at its first level (e.g., at level H); when the second signalreaches its second level (e.g., level L), the output signal E is enabledto undergo a transition from its given level (H) to a second level (L);and then the relatively fast transition 26 in the first signal (waveformC) is used to clock the output signal E to the second level (L). Asdiscussed in more detail below, this technique uses the transition 26which is relatively fast (as opposed to using a speeded-up version theintegrated sensor signal) to develop an output signal E that has but asingle transition (at time T₃) representing the threshold crossing ofthe sensor signal, irrespective of the possible multiple transitionsshown in waveforms C and D.

Turning again to FIG. 3, the flip-flop 46 has a clock input (C)receiving the first signal from node C, and a data input (D) receivingthe second signal from node D. In this embodiment, the set input (S) ofthe flip-flop also receives the signal from node D, and the reset input(R) is grounded. The Q output of the flip-flop provides the outputsignal E.

The flip-flop 46 operates as follows. The output signal E is held at thelevel H until the occurrence of the positive-going transition 26 in theclock signal (waveform C), at which time (T₃) the Q output assumes thestate of the D input. Because the D input is low at T₃, the signal Eundergoes a negative-going transition 48. This transition 48 representsthe threshold crossing 28 in the sensor signal. Note also that theclocking transition 26 occurs while the D input is stable; i.e. multipletransitions in the signal at the flip-flop's D input do not occur at ornear time T₃. Therefore, even if multiple transitions 26 occur inwaveform C, the output signal E will have only one transition 48. Thesingle transition 48 may move somewhat, either to the left or right ofits illustrated position, in response to noise-induced changes in theposition of a transition 26, but only a single transition 48 will bedeveloped.

After the transition 48 occurs, the output signal E is maintained at thelevel L so long as waveform D remains at its level L, irrespective offurther transitions in waveform C. The set input to the flip-flop drivesthe output signal E high again (transition 50) in response to apositive-going transition 44 in waveform D. Having been thus drivenhigh, the signal E is not influenced by possible multiple transitions 32or 44 in waveforms C and D.

The present technique for developing the output signal E is not limitedto the use of D-type flip-flops as shown in FIG. 3. Other types of logiccircuits may be used, or other configurations of D-type flip-flops mayalso be used. One such alternate configuration is shown in FIG. 5. Inthis embodiment, a flip-flop 52 has a Q output that provides the outputsignal E, a set input receiving waveform D, and a clock input receivingwaveform C, all as shown in the embodiment of FIG. 3. In the embodimentof FIG. 5, however, the data (D) input is grounded. This means that thetransition 48 is developed in the manner described for the FIG. 3embodiment, but the transition 50 is generated by the set input goinghigh when the D signal has returned to its level H. As with theembodiment of FIG. 3, the output signal E is free of multipletransitions.

Another embodiment is shown in FIG. 6. Here, a flip-flop 54 has a reset(R) input receiving waveform D, a clock (C) input receiving waveform C,a data input (D) coupled to +5 volts, and a Q output terminal at whichthe waveform E is developed. With this arrangement, a transition 48 isgenerated in the output signal E in response to a positive-goingtransition 26 in waveform C, and a transition 50 is generated inresponse to the reset input being driven high by a transition 44 inwaveform D. This arrangement also eliminates multiple transitions fromthe output signal E.

A feature of the embodiments discussed above is that they all use thethreshold-crossing signal developed by the first signal processor 23 toclock the output signal. Since the output from the first signalprocessor 23 tends to always have a relatively fast transition which canbe reliably used for clocking purposes, there is less need for includingpulse-shaping circuitry in the second signal processor 34 to ensure thatits output includes a fast transition that can be used for clocking.Further, all the embodiments provide an output signal that is free ofmultiple, unwanted transitions, even in the presence of noise on thesensor signal.

Although the invention has been described in terms of preferredstructures, it will be obvious to those skilled in the art that variousalterations and modifications can be made without departing from theinvention. Accordingly, it is intended that all such modifications andalterations be considered as within the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. In a system which processes a sensor signal thathas a threshold-crossing to form: (a) a first signal having a relativelyfast transition that represents the threshold-crossing of the sensorsignal, and (b) a second binary signal that has transitions betweenfirst and second levels and that is representative of an integratedversion of the sensor signal, a method of processing the first andsecond signals to form a binary level output signal, the methodcomprising:(1) holding the output signal at a given level A while thesecond signal is at its first level; (2) when the second signal reachesits second level, enabling the output signal to undergo a transitionfrom the given level A to a second level B, and then (3) using thetransition in the first signal to clock the output signal to the secondlevel B.
 2. A method as set forth in claim 1 further including:(4)maintaining the output signal at the second level B so long as thesecond signal remains at its second level, irrespective of furthertransitions in the first signal.
 3. A threshold-crossing detectorhaving:a sensor for producing a sensor signal having athreshold-crossing; a first signal processing circuit receiving thesensor signal for developing a first signal that has a relatively fasttransition that represents the sensor signal's threshold-crossing; asecond signal processing circuit receiving the sensor signal fordeveloping a second signal that has transitions between first and secondlevels and that is representative of an integrated version of the sensorsignal; and an output circuit receiving the first and second signals fordeveloping an output signal having an amplitude transition thatrepresents the threshold-crossing of the sensor signal; characterized inthat the output circuit comprises a logic circuit having a clock inputreceiving the first signal, and a second input receiving the secondsignal, the logic circuit being responsive to the transition in thefirst signal for driving the output signal rapidly from a first logiclevel to a second logic level, thereby generating an amplitudetransition representing the threshold-crossing of the sensor signal. 4.A threshold-crossing detector as set forth in claim 3 wherein the logiccircuit comprises a flip-flop having a clock input which receives thefirst signal and a data input receiving the second signal.
 5. Athreshold-crossing detector as set forth in claim 4 wherein theflip-flop also has a set input that receives the second signal.
 6. Athreshold-crossing detector as set forth in claim 4 wherein theflip-flop also has a reset input that is coupled to a referencepotential.
 7. A threshold-crossing detector as set forth in claim 3wherein the logic circuit comprises a flip-flop having a clock inputwhich receives the first signal and a reset input that receives thesecond signal.
 8. A threshold detector as set forth in claim 7 whereinthe flip-flop also includes a data input that is coupled to a positivevoltage source.
 9. A threshold-crossing detector for use with a sensorwhose output signal undergoes a threshold-crossing, the detectorcomprising:a first signal processing circuit receiving the sensor signalfor developing a first signal that has a relatively fast transition thatrepresents the sensor signal's threshold-crossing; a second signalprocessing circuit receiving the sensor signal for developing a secondsignal that has transitions between first and second levels and that isrepresentative of an integrated version of the sensor signal; and aflip-flop having an output, a clock input, and a set input, the clockinput receiving the first signal and the set input receiving the secondsignal.
 10. A threshold-crossing detector as set forth in claim 9wherein the flip-flop also includes a data input that receives thesecond signal.